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Interfacing OTG243 USB Host/Function/OTG Controller to MCF5272 ColdFire Processor
Reference Design
TransDimension Inc.
2 Venture Irvine, CA 92618 www.transdimension.com Phone: (949) 727-2020 Fax: (949) 727-3232 sales@transdimension.com techsupport@transdimension.com TDI Document Number: MU2017 Rev. 1.00: September, 2002
TransDimension Inc.
Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
The device and its documentation are provided "as is". Transdimension hereby disclaims all warranties, express, statutory and implied, applicable to the software and its documentation and any related products, including, but not limited to, any warranty of merchantability, noninfringement or fitness for a particular purpose. Transdimension assumes no liability for any act or omission of the licensee. In no event shall Transdimension be liable for direct, special, indirect, incidental, punitive, exemplary or consequential damages, including, without limitation, loss of profits or revenue, loss of products, data or any associated equipment, cost of capital, cost of substituted equipment or parts, facilities or services, down-time or labor costs, even if Transdimension has been advised of the possibility thereof. The device and any related products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. Any such use and subsequent liabilities that may arise from such use are totally the responsibilities of the licensee.
(c) 2002, TransDimension Inc., All rights reserved. All product names are trademarks or registered trademarks of their respective owners.
TransDimension Inc.
Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
Revision History
Version Number 1.00 Release Date September, 2002 Notes First release
Note: This document is subject to change without notice
TransDimension Inc.
Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
Contents
1. Introduction..........................................................................................................................1 1.1 System Overview .....................................................................................................1 1.2 References................................................................................................................2 1.3 Notation....................................................................................................................2 1.4 Software ...................................................................................................................2 Bus Interface ........................................................................................................................3 2.1 Recommendations....................................................................................................3 2.2 Required Procedure..................................................................................................3 2.3 Hardware Design .....................................................................................................3 Operating Mode: /EXVBO and TEST ....................................................................3 Bus Control: /CS, /RD, and /WR.............................................................................4 Address Bus: A8:A2 ..................................................................................................4 Data Bus: D31:D0 .....................................................................................................4 Hardware Reset: /RESET .......................................................................................4 Interrupt: INT..........................................................................................................4 Crystal Oscillator and PLL: OSC1 and OSC2 .........................................................5 DMA: DRQ1, DACK1, EOT1, DRQ2, DACK2, and EOT2 ........................................5 Remote Wakeup: WAKEUP ....................................................................................5 External Pull-Up: RPU............................................................................................5 OverCurrent: /OC....................................................................................................6 Power On: /PO ........................................................................................................6 2.4 Software Configuration............................................................................................6 Bus Cycle Timing .....................................................................................................6 MCF5272 Chip Select Programming ......................................................................7 Software Controlled OTG243 Reset ......................................................................10 Software Controlled Remote Wakeup ....................................................................11 Interrupt: MCF5272 Configuration.......................................................................11 Interrupt: OTG243 Configuration .........................................................................12 USB System Initialization ......................................................................................12 2.5 OTG243 Access .....................................................................................................12 OTG243 Memory Map...........................................................................................12 OTG243 Register Access .......................................................................................14 OTG243 On-Chip Memory Access ........................................................................14 USB Port Circuits ..............................................................................................................15 3.1 OTG243 Port 2 and Port 3 .....................................................................................15 USB Signal Lines ...................................................................................................15 USB Host Power Distribution................................................................................16 3.2 OTG243 Port 1.......................................................................................................16 USB Signals ...........................................................................................................16 VBus Circuit...........................................................................................................16 Software Considerations........................................................................................16 Power and Ground .............................................................................................................16 Reference Design Schematics............................................................................................17 OTG243 Module for uCevolution Development Platform...............................................17
2.
3.
4. 5. 6.
TransDimension Inc.
Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
7.
Technical Support ..............................................................................................................19
TransDimension Inc.
Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
1. Introduction 1.1 System Overview
TransDimension's OTG243 is a low cost, high-performance, easily programmable device designed specifically for embedded USB host, USB function, and USB On-The-Go (OTG) dual role device (DRD) applications. It can be configured to operate as: A standard USB OTG DRD controller (Port 1) and a standard USB 2-port host controller (Port 2 and Port 3). A standard USB 2-port host controller (Port 2 and Port 3), and a standard USB function controller (Port 1). A standard USB 3-port host controller (Port 1, Port 2 and Port 3). The chip is designed for the embedded USB applications, especially mobile and post-PC products, including cell phones, palm platforms, personal digital assistants, set top boxes, home gateway systems, and Internet appliances. Peer-to-Peer communication is made simple with the OTG243 as USB connectivity may be achieved without the intervention of a personal computer. The block diagram for the OTG243 is shown below.
OSC1 OSC2 CEX1 CEX2 VFB VBUS VBP
PLL PSC
48 MHz 12 MHz System Configuration & Control Registers PSH USB Function Controller Registers USB Function Control Logic PSH USB Host Control Logic Host SIE & Root Hub PSF Function SIE
Charge Pump & VBus Control Circuit
/RESET /CS /WR /RD DRQ1 DACK1 EOT1 DRQ0 DACK0 EOT0 A8:A2 D31:D0 INT WAKEUP /EXVBO TEST
HNP/ SRP Logic H/F OTG Transceiver USB Transceiver USB Transceiver
ID
P Interface
RPU DM1 DP1 DM2 DP2 DM3 DP3
Memory Blocks
Test Control
USB Host Controller Registers
/PO
/OC
Figure 1: OTG243 block diagram 1
TransDimension Inc.
Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
NC D0 D1 D2 VDD VDD D3 D4 D5 D6 D7 VSS D8 D9 D10 D11 D12 D13 D14 D15
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VDD VDD VSS TEST NC /CS /WR /RD D16 D17 D18 D19 D20 D21 D22 D23 VDD VSS D24 D25
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
D26 D27 VSS VDD DP2 DM2 DP3 DM3 NC NC NC RPU DP1 DM1 VSS D28 D29 D30 D31 VSS
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
VDD VDD WAKEUP INT /RESET VBP A2 A3 A4 A5 A6 A7 A8 NC NC AVDD AVSS CEX1 VDD CEX2
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
VBUS VFB /OC /PO ID VSS VDD VDD /EXVBO DRQ1 DRQ0 DACK1 DACK0 EOT1 EOT0 VSS AVSS OSC1 OSC2 AVDD
Figure 2: OTG243 pin assignment (LQFP) 1.2 References
General instructions on OTG243 interfacing are given in chapters 6 and 7 of the OTG243 data sheet (TDI document number: MU2001). This reference design describes a specific interfacing design of OTG243 with Motorola MCF5272 ColdFire. It is assumed that the user has knowledge on general principles of microprocessor interfacing, as well as some understanding on the Motorola MCF5272 and the OTG243. Reading Chapter 7 of USB Specification 2.0 is recommended. 1.3 Notation
For clarity, all OTG243 signal names in the following are in italic bold: e.g., A4 and VBUS, and active low signals are written with leading "/": e.g., /WR. MCF5272 names are in plain bold: e.g., A4 and nCS0, and active low signals are written with leading "n": e.g, CS0 is written as nCS0. 1.4 Software
TransDimension, together with SoftConnex Inc, its wholly owned subsidiary, offer total solutions including controller chips, reference designs, development kits, firmware for microprocessor interfacing, HCD (host controller driver), HNP (Host Negotiation Protocol), SRP (Session Request Protocol) as well as USB Host and Function stacks running under most real time operating systems. 2
TransDimension Inc.
Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
2. Bus Interface 2.1 Recommendations
For the MCF5272, we recommend that: The OTG243 is interfaced directly to MCF5272's system bus. The OTG243 operates in 16-bit mode (pin /EXVBO pulled-down). This reference design has been tested in 16-bit mode, but should work just as well in 32-bit mode. The OTG243 is accessed through the MCF5272 chip-select as memory-mapped peripheral. Any of the chip-select signals nCS[5:2] can be programmed for an address location, with masking capabilities, port size, burst capability indication, and wait-state generation. nCS2 is used for this reference design. The chosen chip-select is programmed to 16-bit access with a bus cycle compatible to that of the OTG243's. The above recommendations are assumed throughout this document. Alternative interfacing schemes, such as 32-bit access to the OTG243, can function just as well. 2.2 Required Procedure
MCF5272 operates under big endian mode, but OTG243 operates under the little endian mode. Software is required to perform byte swapping for the data. 2.3 Hardware Design
This sub-section discusses hardware aspects of interfacing the OTG243 to the MCF5272. Software considerations are presented in Section 2.3. The following signals of the OTG243 are involved in the bus interfacing. For simplicity and clarity, buffers are not inserted between the MCF5272 and the OTG243. One should use his/her own judgment on this issue based on a specific application. Operating Mode: /EXVBO and TEST /EXVBO should be pulled down for 16-bit operation, and the TEST pin must be grounded.
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Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
Bus Control: /CS, /RD, and /WR In this reference design, the OTG243 is accessed through MCF5272's nCS2 (base memory address 40000000). Thus OTG243 chip select /CS, read strobe /RD, and write strobe /WR should be tied to nCS2, nOE/RD, and R/nW of the MCF5272, respectively.
Address Bus: A8:A2 The OTG243 address bus A8:A2 is connected to A8:A2 of the MCF5272. Data Bus: D31:D0 The lower 16-bit data bus of the OTG243 D15:D0 should be connected to D31:D16 of the MCF5272. This is due to MCF5272 data bus D15:D0 becoming GPIO port C when configured as 16-bit external data bus. The upper 16-bit data bus of the OTG243 D31:D16 should be pull-down with 15K resistors. Hardware Reset: /RESET For many applications, the OTG243 /RESET can be tied to MCF5272's system reset (nRSTI or nRSTO). However, it is recommended that a MCF5272 GPIO pin be allocated as the OTG243 hardware reset for flexibility of user software. In this reference design, PC12 (GPIO Port C bit 12) of the MCF5272 is assigned to the OTG243's /RESET, and its selection depends on the application. To improve reliability, a pullup resistor is desired. An RC filter circuit is highly recommended to eliminate unexpected noise triggered reset. Interrupt: INT The interrupt signal INT generated by the OTG243 must be tied to one of the six nINTn pins of the MCF5272. In this reference design, MCF5272 pin nINT2 is employed, and its selection again depends on the application. Note that the active level (active high or active low) and the output type (totem-pole or wired OR) of the OTG243 INT pin are programmable. For this reference design, the OTG243 INT pin is to be programmed to active low, totem-pole operation. A pull-up resistor is recommended.
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Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
Crystal Oscillator and PLL: OSC1 and OSC2 In the reference design, a 6 MHz parallel resonance quartz crystal is connected across OSC1 and OSC2. The following circuit is recommended.
6.000 MHz 6.8 pF 6.8 pF OSC2 OTG243 OSC1 100
Figure 3: OTG243 crystal oscillator circuit To meet the USB frequency accuracy and stability requirements, the crystal should have an accuracy and stability better than 200 ppm. For a 6 MHz resonance quartz crystal, the recommended ESR value should be less than 100 . DMA: DRQ1, DACK1, EOT1, DRQ2, DACK2, and EOT2 In this reference design, DMA is not tested and not supported. When these signals are not used, proper connections should be made by pulling up or down according to the application. The logic levels of DRQ1 and DRQ2 at the time of hardware reset determine the frequency of the oscillation imposed on the OSC1 and/or OSC2 pins. In this reference design, a 6 MHz crystal is employed. Therefore the DRQ1 and DRQ2 should be tied with pull-down resistors smaller than 10k. Since DACK1, DACK2, EOT1, and EOT2 signals are all configured as inputs and active low signals right after reset, they should be pulled-up by resistors. Note: Even though the MCF5272 has a one-channel DMA controller internal to MCF5272, which supports memory-to-memory DMA transfers that can be used for block data moves, it does not require any external signals for DMA transfer. It uses normal memory access signals for DMA transfer. Remote Wakeup: WAKEUP This pin is only meaningful if Port 1 of the OTG243 is assuming the role of a USB function. In this reference design, a MCF5272 GPIO pin (PC13) is assigned to it. Since WAKEUP is active high, a pull-down resistor is recommended. External Pull-Up: RPU If the internal pull-up resistor does not satisfy the USB 1.5K pull-up tolerance, an external 1.5K +/- 1% can be connected from RPU signal to DP1 signal. 5
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Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
This pin should be left floating if external 1.5K pull-up resistor is not used. OverCurrent: /OC It is recommended to add an external pull-up for OverCurrent signal. Power On: /PO This ganged power-on signal is an output, so it is OK to leave it floating if not used. However, do not use pull-up resistor if this signal is used in a low power application. If OTG243 is put into power-save mode with /PO signal asserted, there will be unnecessary current leakage through this pull-up resistor. 2.4 Software Configuration Bus Cycle Timing Bus cycle timing parameters for the OTG243 read/write operation are listed below. The OTG243 register read and register write cycles are illustrated in Figures 5 and 6, respectively.
Symbol tRPW tWPW tACR tASL tAHH tDSW tDVR tDHR tDHW tCRWL tRWCH Parameter /RD pulse width /WR pulse width Access cycle recovery time Address setup time before /RD or /WR goes low Address hold time after /RD or /WR high Data setup time before /WR high Data valid time after /RD low Data hold time after /RD high Data hold time after /WR high /CS low to /RD or /WR low /RD or /WR high to /CS high Min 55 55 25 0 0 45 0 0 0 Max Unit ns ns ns ns ns ns ns ns ns ns ns
55 3
Figure 4: OTG243 bus cycle timing parameters
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Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
tCRWL CS
tRPW
tACR tRWCH
RD A8:A2 tASL D15:D0 tDVR valid data tDHR valid address tAHH
Figure 5: OTG243 register read cycle
tCRWL CS tRWCH WR A8:A2 tASL D15:D0 valid data tDSW tDHW valid address tWPW tACR
tAHH
Figure 6: OTG243 register write cycle MCF5272 Chip Select Programming Based on the OTG243 register read/write cycle specification, the chip select base registers (CSBR2) and the chip select option registers (CSOR2) for nCS2 may be programmed according to the following:
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Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
CSBR2 Addr : 0x050 Default value after reset : 0x0000_2300
Field BA EBI BW SUPER TT TM CTM ENABLE Bits 31:12 11:10 9:8 7 6:5 4:2 1 0 Function Base Address. External bus interface modes. Bus width. Supervisor mode. Transfer type. Transfer modifier. Compare TM. Enable Settings 4000_0 00 10 0 00 000 0 1 Meaning Starting address 16/13-bit SRAM/ROM Word (16 bits) User or Supervisor mode Don't care, since CTM is not set. Don't care, since CTM is not set. TT & TM register bits do not affect address match. CS2 enabled Default 0000_2 00 11 0 00 000 0 0
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Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
CSOR2 Addr : 0x054 Default value after reset : 0xFFFF_F078
Field BAM ASET Bits 31:12 11 Function Address mask Address setup enable Settings FFFF_F 1 Meaning Compare address bits Delay assertion of chip select for one CLK cycle after address is asserted. During write transfers, both chip select and R/nW are delayed by 1 clock cycle. Hold address, data, and attribute signals an extra cycle after nCS2 and R/nW negate on writes Hold address and attribute signals an extra cycle after chip select negate on reads. Vailid only for nCS7. 3 wait states Don't care since MRW is cleared. Memory covered by chip select is read/write Default FFFF_F 0
WRAH
10
RDAH
9
EXTBURST WS RW
8 7 6-2 1
Controls the address, data and attribute hold time after the termination, internal or external with /TA, of a write cycle that hits in the chip select address space. Controls the address and attribute hold time after the termination, internal or external with /TA, of a read cycle that hits in the chip select address space. Enable extended burst. Reserved, should be cleared. Wait state generator RW and MRW determine whether the selected memory region is read only or write only. MRW must be set for value of RW be taken into consideration.
1
0
1
0
00011 0
0 0 11110 0
MRW
0
0
0
PBCNT Addr : 0x088 Default value after reset : 0x0000_0000
Field PBCNT5 Bits 11:10 Function Port B Control Regitster. PB5/nTA select Settings 00 Meaning Select PB5 Default 00
Figure 7: MCF5272 register CSBR2, CSOR2, & PBCNT settings to generate nCS2 9
TransDimension Inc.
Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
104 ns CS RD 20.8 ns A8:A2 valid address
> 104 ns
> 20.8 ns
Figure 8: MCF5272 bus read cycle generated using parameters of Figure 7
104 ns CS WR 20.8 ns A8:A2 valid address
> 62.4 ns
> 20.8 ns
Figure 9: MCF5272 bus write cycle generated using parameters of Figure 7 The memory map of nCS2 is determined by 2 parameters. The content of BA field in CSBR2 register determines the starting address of the nCS2. The content of BAM field in CSOR2 register determines the memory block size of nCS2. In this design the starting address is set to 0x40000000, and the block size is set 4K byte. The wait states are controlled by the combination of ASET, WRAH, RDAH, and WS fields in CSOR2 register. In this design, ASET, WRAH, and RDAH are set and WS is set to 3 wait states. Also, the transfer acknowledge (nTA) signal is not utilized but this signal is assigned as GPIO port PB5 in this reference design. Note that these settings are based on the assumption that the MCF5272 is running at an external 48 MHz oscillator. They are set for the MCF5272 to generate near-optimal access cycles satisfying the OTG243 specification. It is advised that one starts with a much looser (slower) set of timing parameters, such as 1FH, applied to the WS field of this CSOR2 register, and then have them fine-tuned towards optimal performance. Software Controlled OTG243 Reset
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Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
It is assumed that PC12 of the MCF5272 is employed to support software controlled /RESET for the OTG243. The MCF5272 GPIO registers should be initialized according to Figure 12.
Register PCDDR PCDAT Address 0x0094 0x0096 Register Full Name Port C Data Direction Register Port C Data Register Bit 12 1 1 Meaning output no reset Default 0 undefined
Figure 12: MCF5272 GPIO register settings to support software generated /RESET To issue an OTG243 reset through software, one must Step 1: Write to GPIO register PCDAT with a bit pattern such that Bit 12 = 0. This asserts the active low OTG243 pin /RESET. Step 2: Wait for at least 40 s. Step 3: Write to GPIO register PCDAT with a bit pattern such that Bit 27 = 1. This de-asserts the active low OTG243 pin /RESET. Software Controlled Remote Wakeup It is assumed that PC13 of the MCF5272 is employed to support software controlled /WAKEUP for the OTG243 function operation. The MCF5272 GPIO registers should be initialized according to Figure 13.
Register PCDDR PCDAT Address 0x0094 0x0096 Register Full Name Port C Data Direction Register Port C Data Register Bit 13 1 0 Meaning output no wakeup Default 0 undefined
Figure 13: MCF5272 GPIO register settings to support software generated WAKEUP To issue a remote wakeup to the OTG243 through software, one must Step 1: Write to GPIO register PCDAT with a bit pattern such that Bit 13 = 1. This asserts the active high OTG243 WAKEUP. Step 2: Wait for at least 1 s. Step 3: Write to GPIO register PCDAT with a bit pattern such that Bit 13 = 0. This de-asserts the active high OTG243 WAKEUP. Interrupt: MCF5272 Configuration In the following discussion, it is assumed that nINT2 of the MCF5272 is connected to OTG243's INT pin, which has been programmed to be active low with totem-pole output. The MCF5272's interrupt control registers should be initialized as follows: 11
TransDimension Inc.
Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
Register ICR1 PITR
Address 0x020 0x034
Register Full Name Interrupt Control Register 1 Programmable Interrupt Transition Register
Bits 27:24 30
Bit Values 1011 0
Meaning Interrupt priority level Negative edge triggered
Default 0000 0
Figure 14: MCF5272 GPIO register settings to support OTG243 interrupt Please note that the interrupt generated by the OTG243 is level sensitive. Caution must be taken when it is interfaced with an interrupt controller, such as the one in the MCF5272, that supports only edge-sensitive interrupt sources. Interrupt: OTG243 Configuration The software must configure the OTG243 before the MCF5272 enables the interrupt originated from it. The following steps must be carried out: Step 1: Configure the OTG243 INT pin to be active low. This requires Bit 16 of the OTG243 HardwareMode Register (000H) be set to 0, which is the default. Step 2: Configure the OTG243 INT pin to be totem-pole output. This requires Bit 21 of the IOConfiguration2 Register (04CH) to be set to 1 by user software. Note that the INT pin defaults to wired OR output, which should also work if a pull-up resistor is present. Step 3: Enable interrupt sources on the OTG243 side, which involves four sets of registers as described in detail in Section 7.4 of the OTG243 Data Sheet. USB System Initialization It should be emphasized that all MCF5272 register settings and the OTG243 hardware system settings discussed above must be completed before the USB controllers within the OTG243 are activated. 2.5 OTG243 Access OTG243 Memory Map The OTG243 control registers and internal memory blocks are accessed through a two-level memory map as shown in Figure 9. It should be emphasized that all registers and data accesses are in 32-bit double word (DWORD), even if the OTG243 is placed on a 16-bit bus. In the latter case, a pair of 16-bit accesses (first for the least significant 16-bits, and the second for the most significant two bytes) must be issued successfully by the microprocessor for reading or writing a single DWORD. Thus the least significant two bits of the address bus (A1 and A0) are always treated as 00b. 12
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Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
The MCF5272 communicates with the OTG243 through the Primary Memory Map (PMM), consisting of 128 DWORD registers. Thus all OTG243 accesses to the OTG243 are register reads or register writes. In other words, the microprocessor does not access the OTG243's internal memories. The ETD Memory (128 DWORDs) and the Data Memory (1K DWORDs) inside the OTG243 are accessed through an address register named MemoryAccessStartAddress Register (0A4H), and a data port register called PIODataPort Register (02CH) using the standard two-stage access methodology. If the MemoryAccessType bit (Bit 15 of the MemoryAccessStartAddress register) is 0, the ETD Memory is accessed. Otherwise, the Data Memory is read from or written into. It must be emphasized that the address specified in the MemoryAccessStartAddress register is in DWORDs, not in bytes, relative to the beginning of the ETD Memory or the Data Memory, respectively. Using burst read and burst write, the OTG243 supports fast data movement between the microprocessor and on-chip memory.
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MCF527 Registers 512 bytes
000H 004H : 02CH : 0A4H : 1FCH
: : : PIODataPort : : :
Bit 15 = 0
ETD0 ETD1 ETD2 : : ETDF Reserved
0000H 0008H 0010H : : 0078H 0080H
ETD Memory 128 DWORDs
Reserved 7FFFH 8000H 8001H : : 83FFH 8400H
Primary Memory Map (512 bytes) MemAccessStartAddress Register
Bit 15 = 1
data data : : data
Data Memory 1K DWORDs
Secondary Memory Map (64K DWORDs)
Reserved FFFFH
Reserved
Figure 9: OTG243 memory map OTG243 Register Access In this reference design, the physical address used by the MCF5272 to access OTG243 address m in its PMP is 40000000H + m, where 000H m 1FFH. Note that the least significant two bits of m are always treated as 00B. OTG243 On-Chip Memory Access The ETD Memory (128 DWORDs) and Data Memory (1K DWORDs) can be accessed through a procedure called Programmed I/O (PIO), which is carried out as follows: Step 1: Write into MemoryAccessStartAddress Register an access word indicating (i) memory segment - either ETD Memory or Data Memory; (ii) access address - offset to the beginning of the memory segment indicated in (i). Note that the unit of this address is DWORDs, not bytes; and (iii) intended access direction - Read or Write. Formats of the access word for the ETD Memory and that for the Data Memory are given in Figures 10 and 11, respectively.
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Bit 8:0 14 15 13:9, 31:16
Description Address (relative to the beginning of the respective memory) in DWORDs. Access direction. 1 for write and 0 for read. Selection between ETD memory (0) and data memory (1). Reserved. Should be filled with 0's.
Figure 10: ETD Memory access word
Bit 11:0 14 15 13:12, 31: 16 Description Address (relative to the beginning of the respective memory) in DWORDs. Access direction. 1 for write and 0 for read. Selection between ETD memory (0) and data memory (1). Reserved. Should be filled with 0's.
Figure 11: Data Memory access word Step 2: Wait until the PIO channel is ready by examining the PIOReady bit (Bit 0) of the PIOReady Register (044H). Continue to Step 3 only after the bit has become low. Step 3: Write into, or read from the PIODataPort register (02CH) for one DWORD, or a block of consecutive DWORDs. In the latter case, the accessing address is increased automatically. The access direction (read/write) in this step should be consistent with that specified in the access word. (If not, the access direction indicated in the access word takes precedence.) 3. USB Port Circuits This section discusses circuits between the USB ports of the OTG243 and their connectors. Note that these issues are generic and in fact independent to that of the MCF5272 interfacing. One should consult Chapter 7 of the USB specification 2.0, as well as Chapters 6 and 7 of the OTG243 data sheet for details. 3.1 OTG243 Port 2 and Port 3 These two ports can only serve as standard downstream host ports. Thus they use USB Type A receptacles. USB Signal Lines Two 15 k pull-down resistors are required on the DPn and DMn (n = 2, 3) data lines to support detection of a device connecting or disconnecting event. To satisfy the impedance matching requirement, a 33 resistor should be inserted between a USB data line (DPn or DMn) and its corresponding pin at the USB Type A connector.
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Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
If a port is not used, its DMn and DPn pins must be pulled down via 15 k resistors. They cannot be grounded directly or be left floating. USB Host Power Distribution In this reference design, TI's dual power-distruibution switch TPS2042 is employed. When the current flowing through this device exceeds the current-limit threshold (0.9A) or a short is present, the /OC pin of the OTG243 is asserted. As an alternative, a poly-switch resettable device (nanoSMD100, specially made by RayChem/Tyco for USB applications) can be used. A sufficiently large capacitor (more than 120 F) is applied to the VBus of each port, per USB specification. Ferrite beads are inserted in the VBus and ground circuits for EMI reduction. 3.2 OTG243 Port 1
This port can be configured as a standard USB host port, a standard USB function port, or an OTG port. The details are given in Section 6 of the OTG243 data sheet. In this reference design, Port 1 serves as a port for a USB OTG dual role device. USB Signals The USB signal circuits for Port 1 (DM1, DP1) are similar to that of Port 2 and Port 3, except that the two pull-down resistors are integrated with the OTG transceiver circuit. In addition, this reference design chooses the internal pull-up resistor when the OTG243 assumes the role of a full speed USB function. VBus Circuit In the reference design, the internal charge pump is used as the Vbus power source. As an ADevice, it supplies the power of 5V of up to 12 mA. As a B-Device, it is the power source for "VBus pulsing". A capacitor of 0.47 F must be connected between OTG243 pins CEX1 and CEX2. Two 2.2 F capacitors and a 10 H inductor constitutes a low pass filter for the charge pump output. A 10 resistor and a 1 F capacitor serve as part of the voltage feedback. Software Considerations Operating as a USB OTG controller, the OTG243 implements the HNP/SRP (Host Negotiation Protocol and Session Request Protocol), which configures Port 1 circuit dynamically. For details, please contact TransDimension technical support for details. 4. Power and Ground
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The chip can be used with a single DC power supply of 3.3V. VDD and AVDD should be connected at only one point on a printed circuit board. This also applies to VSS and AVSS. All logic I/O pins are LVCTTL compatible, and 5V tolerant. 5. Reference Design Schematics The schematic drawing on Page 14 is based on several assumptions made in the above discussion. It must be modified according to one's application. 6. OTG243 Module for uCevolution Development Platform TransDimension has developed an OTG243 module (CXB243) that can be plugged into the soDIMM bus of the uCevolution Development Platform with uCdimm ColdFire 5272 Microcontroller Module, allowing quick OTG243 evaluation and user software development. Contact TDI technical support for details.
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TransDimension Inc.
3.3V R1 4.7Kx4 R2 100 C2 6.8 pf Y1 6 MHz 98 C3 6.8 pf 99 65 26 27 28 A8 A7 A6 A5 A4 A3 A2 R7 R8 R9 R10 R11 R13 R14 R15 R16 R18 R19 R20 R21 R22 R23 R24 15K 15K 15K 15K 15K 15K 15K 15K 15K 15K 15K 15K 15K 15K 15K 15K 73 72 71 70 69 68 67 59 58 57 56 42 41 40 39 36 35 34 33 32 31 30 29 20 19 18 17 16 15 14 13 11 10 9 8 7 4 3 2 90 92 94 91 93 95 CF_nINT2 CF_PC13 64 63 89 24 VBUS VFB VBP RPU DM1 DP1 ID PO U1 OSC1 OTG243_LQFP100 CEX1 CEX2 C1 0.47 uF
Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
78 80 81 82 66 52 54 53 85 84 5V
L1 R3 10 C4 2.2 uF
10 uH C5 2.2 uF L2 1 2 3 4 5 6 J1 MINI-AB
CF_PC12 CF_nCS2 CF_nOE/RD CF_R/nW C7 22pF
R4
130
OSC2 RESET CS WR RD A8 A7 A6 A5 A4 A3 A2 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DRQ1 DACK1 EOT1 DRQ0 DACK0 EOT0 INT WAKEUP EXVBO TEST
C6 1.0 uF
R5
33x2
B
C8 2200 pF
3 4 R6 4.7K 8 5
EN1 EN2
IN GND
2 1 7 6
5V C10 33 uF
C11
C9
B
0.01 uF
L3 0.01 uF
+5V DD+ ID GND SHLD
CF_A[8:2]
OC
83
OC1 OUT1 OC2 OUT2 U2 TPS2042D
L4
B
DM2 DP2
46 45
R12
33x2
B
R17 39x2
C12 150 uF
C13 0.01 uF
L5
1 2 3 4 5
J2
USB-A
+5V DD+ GND SHD
L6 DM3 DP3 VDD5 VDD6 VDD21 VDD22 VDD37 VDD44 VDD61 VDD62 VDD79 VDD87 VDD88 VSS12 VSS23 VSS38 VSS43 VSS55 VSS60 VSS86 VSS96 AVDD76 AVDD100 AVSS77 AVSS97 48 47 5 6 21 22 37 44 61 62 79 87 88 12 23 38 43 55 60 86 96 76 100 77 97 A3.3V Title Size A Date: R25 33x2
B
CF_D[31:16] 3.3V
R27 4.7Kx8
R28 4.7Kx2
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
B
R26 39x2
C14 150 uF
C15 0.01 uF
L7
1 2 3 4 5
J3
USB-A
+5V DD+ GND SHD
A3.3V 3.3V 3.3V C16 0.1 uF C17 0.1 uF C18 0.1 uF C19 0.1 uF R29 0 C20 1000 pF C21 0.1 uF
TransDimension Inc.
OTG243:MCF5272 ColdFire Reference Design Document Number SC-OTG243-A6.1-001 Monday, September 16, 2002 Sheet 1 of 1 Rev 1.0
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TransDimension Inc.
Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
7. Technical Support Technical questions should be addressed to: Technical Support TransDimension Inc. 2 Venture Irvine, CA 92618, USA +1 (949) 727-2020 x242 (phone) +1 (949) 727-3232 (fax) Email: techsupport@transdimension.com
For additional information, contact your TransDimension Sales Representative or the following: INTERNET: E-MAIL: Headquarters: America: Japan: http://www.transdimension.com sales@transdimension.com, techsupport@transdimension.com. TransDimension Inc., 2 Venture, Irvine, CA 92618, USA. Tel: +1(949) 727-2020, Fax: +1(949) 727-3232 Pete Todd, VP of Sales, E-mail: ptodd@transdimension.com TransDimension Inc., 815 West Market St., Suite 804, Louisvile, KY 40202, USA. Tel:+1(502)992-3226 Larry Hayden, E-mail: lhayden@transdimension.com TransDimension Inc., OYA Bldg. 5, 3 Chome-9-6, Nishishinjuku, Shinjuku-ku, Tokyo, Japan. Tel: +81(3) 5308-7525, Fax: +81(3) 5308 7526 Masanori Sugane, E-mail: sugane@alto.ocn.ne.jp.
Asia (excluding Japan): TransDimension Inc., 3 Ubi Ave 3, #05-01 Crocodile House, Singapore, 408857. Tel: +65 6743 9179, Fax +65 6741 4393 T. L. Nge, E-mail: tlnge@transdimension.com Europe: TransDimension Inc., 7 The Orchard, Hilton, Derbyshire, UK, DE65 5JF. Tel: +44 1283 730045, Fax: +44 1283 730651 Neil Huntingdon, E-mail: nhuntingdon@transdimension.com
Worldwide Reps.: See detailed listing for your area TransDimension representative by viewing http://www.transdimension.com. _____________________________________________________________________________________________________________________________________
(c) 2002, TransDimension Inc. All Rights Reserved Printed in USA August, 2002
MU2017, Rev. 1.00
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